The present invention relates to semiconductor memory devices such as ferroelectric memory devices, and more particularly to a packaging technology in which a plurality of semiconductor chips are laminated, thereby achieving a three-dimensional mounting to multiply a per area memory capacity by the number of layers of the laminated chips, and a technology that makes it possible to optionally select each of the chip layers.
Laminating a plurality of semiconductor chips is known to make a semiconductor integrated circuit to have a higher density. In order to drive the laminated semiconductor chips, it is necessary to provide a structure for selecting as to which one of the chips in the layers is made active. For example, Japanese Laid-open Patent Application HEI 5-63138 describes a structure in which one ends of lead lines are connected to semiconductor chips laminated on a carrier substrate, respectively, and the other ends of the lead lines are connected to conductive pins provided standing on the carrier substrate.
[Patent Document 1] Japanese Laid-open Patent Application HEI 5-63138.
However, the structure described in the aforementioned Japanese Laid-open Patent Application HEI 5-63138 is complex because the laminated chips need to be connected individually to the lead lines and the conductive pins, respectively, which increase the number of wirings and the number of components.
To avoid such problem, each of the chips may be provided with a structure that can be discriminated from the other chips. However, to discriminate the chips one from the other, different kinds of chips need to be manufactured. In this case, there are problems, such as, a lack of economy, because different metal masks are required for manufacturing different chips, and if the yield of chips only in one type is lower, the other chips may remain as excesses.
It is an object of the present invention to solve the problems of the conventional technology described above, and provide laminated type semiconductor memory devices that can improve the yield of chips without complicating wirings and components.